The SIFT chip is an ASIC that was developed for the D0 Experiment at Fermilab. It is an 18 channel chip that is used as the front-end for Visible Light Photon Counters (VLPCs) which are used for reading out the scintillating fibers in the central D0 tracker.

Engineering: Gene Atlas (Adept IC Design), Britt Holbrook and Mani Tripathi.
The SIFT chip amplifies the input charge, and outputs a discriminated signal for each channel. A charge signal is fed into the input of SVX-IID chips. A simplified schematic shows the basic operations of the chip.

Shown below are photographs of a multi-chip module (MCM) consisting of 4 SIFT chips and an SVX-IID chip and an enlarged view of the SIFT chip die.

SIFT MCM SIFT Chip

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